/* 
 * Copyright (C) 2013, 2014 lex xiang
 *
 * file:	include/s2c2440.h
 * history:	2013 July 5 created by lex xiang
 * comment:	more details of cpu
 */


#ifndef __S3C2440_H__
#define __S3C2440_H__

#define REG32(addr)		(*(volatile unsigned int *)(addr))
#define REG8(addr)		(*(volatile unsigned char *)(addr))

#define NR_UART_CHANNELS	3
#define NR_SPI_CHANNELS		2
/* 
 * s3c2440 device base addresses 
 */
#define MEMCTL_BASE_ADDR	0x48000000
#define USB_HOST_BASE_ADDR	0x49000000
#define INT_BASE_ADDR		0x4A000000
#define DMA_BASE_ADDR		0x4B000000
#define CLK_BASE_ADDR		0x4C000000
#define LCD_BASE_ADDR		0x4D000000
#define NAND_BASE_ADDR		0x4E000000
#define UART_BASE_ADDR		0x50000000
#define TMR_BASE_ADDR		0x51000000
#define USB_DEV_BASE_ADDR	0x52000140
#define CE_PHYS_ADDR		0x52000000
#define WTG_BASE_ADDR		0x53000000
#define I2C_BASE_ADDR		0x54000000
#define I2S_BASE_ADDR		0x55000000
#define GPIO_BASE_ADDR		0x56000000
#define RTC_BASE_ADDR		0x57000000
#define ADC_BASE_ADDR		0x58000000
#define SPI_BASE_ADDR		0x59000000
#define SDI_BASE_ADDR		0x5A000000

/*
 * memory control
 */
#define MC_BWS_CTRL  		0x48000000	/* Bus width & wait status     */
#define MC_BANK_CTRL0		0x48000004	/* Boot ROM control	       */
#define MC_BANK_CTRL1		0x48000008	/* BANK1 control	       */
#define MC_BANK_CTRL2		0x4800000c	/* BANK2 cControl	       */
#define MC_BANK_CTRL3		0x48000010	/* BANK3 control	       */
#define MC_BANK_CTRL4		0x48000014	/* BANK4 control	       */
#define MC_BANK_CTRL5		0x48000018	/* BANK5 control	       */
#define MC_BANK_CTRL6		0x4800001c	/* BANK6 control	       */
#define MC_BANK_CTRL7		0x48000020	/* BANK7 control	       */
#define MC_REFRESH 		0x48000024	/* DRAM/SDRAM refresh	       */
#define MC_BANK_SIZE		0x48000028	/* Flexible Bank Size	       */
#define MC_MRSRB6  		0x4800002c	/* Mode register set for SDRAM */
#define MC_MRSRB7  		0x48000030	/* Mode register set for SDRAM */

/*
 * interrupt control
 */
#define INT_REQ_STATUS		0x4a000000	/* Interrupt request status        */
#define INT_MODE_CTRL		0x4a000004	/* Interrupt mode control	   */
#define INT_MASK_CTRL		0x4a000008	/* Interrupt mask control	   */
#define INT_PRIO_CTRL		0x4a00000c	/* IRQ priority control		   */
#define INT_INT_PND		0x4a000010
#define INT_SRC_OFFSET		0x4a000014	/* Interruot request source offset */
#define INT_SUB_SRC_PND		0x4a000018	/* Sub source pending		   */
#define INT_SUB_MASK		0x4a00001c	/* Interrupt sub mask              */

/*
 * DMA control
 */
#define DMA0_INIT_SRC		0x4b000000	/* DMA 0 Initial source		     */
#define DMA0_INIT_SRC_CTRL	0x4b000004	/* DMA 0 Initial source control	     */
#define DMA0_INIT_DST		0x4b000008	/* DMA 0 Initial Destination	     */
#define DMA0_INIT_DST_CTRL	0x4b00000c	/* DMA 0 Initial Destination control */
#define DMA0_CTRL      		0x4b000010	/* DMA 0 Control		     */
#define DMA0_STATUS    		0x4b000014	/* DMA 0 Status			     */
#define DMA0_CURR_SRC  		0x4b000018	/* DMA 0 Current source		     */
#define DMA0_CURR_DST  		0x4b00001c	/* DMA 0 Current destination	     */
#define DMA0_MASK_TRIGGER	0x4b000020	/* DMA 0 Mask trigger		     */

#define DMA1_INIT_SRC		0x4b000040	/* DMA 1 Initial source		     */
#define DMA1_INIT_SRC_CTRL	0x4b000044	/* DMA 1 Initial source control	     */
#define DMA1_INIT_DST		0x4b000048	/* DMA 1 Initial Destination	     */
#define DMA1_INIT_DST_CTRL	0x4b00004c	/* DMA 1 Initial Destination control */
#define DMA1_CTRL      		0x4b000050	/* DMA 1 Control		     */
#define DMA1_STATUS    		0x4b000054	/* DMA 1 Status			     */
#define DMA1_CURR_SRC  		0x4b000058	/* DMA 1 Current source		     */
#define DMA1_CURR_DST  		0x4b00005c	/* DMA 1 Current destination	     */
#define DMA1_MASK_TRIGGER	0x4b000060	/* DMA 1 Mask trigger		     */

#define DMA2_INIT_SRC		0x4b000080	/* DMA 2 Initial source		     */
#define DMA2_INIT_SRC_CTRL	0x4b000084	/* DMA 2 Initial source control	     */
#define DMA2_INIT_DST		0x4b000088	/* DMA 2 Initial Destination	     */
#define DMA2_INIT_DST_CTRL	0x4b00008c	/* DMA 2 Initial Destination control */
#define DMA2_CTRL      		0x4b000090	/* DMA 2 Control		     */
#define DMA2_STATUS    		0x4b000094	/* DMA 2 Status			     */
#define DMA2_CURR_SRC  		0x4b000098	/* DMA 2 Current source		     */
#define DMA2_CURR_DST  		0x4b00009c	/* DMA 2 Current destination	     */
#define DMA2_MASK_TRIGGER	0x4b0000a0	/* DMA 2 Mask trigger		     */

#define DMA3_INIT_SRC		0x4b0000c0	/* DMA 3 Initial source		     */
#define DMA3_INIT_SRC_CTRL	0x4b0000c4	/* DMA 3 Initial source control	     */
#define DMA3_INIT_DST		0x4b0000c8	/* DMA 3 Initial Destination	     */
#define DMA3_INIT_DST_CTRL	0x4b0000cc	/* DMA 3 Initial Destination control */
#define DMA3_CTRL      		0x4b0000d0	/* DMA 3 Control		     */
#define DMA3_STATUS    		0x4b0000d4	/* DMA 3 Status			     */
#define DMA3_CURR_SRC  		0x4b0000d8	/* DMA 3 Current source		     */
#define DMA3_CURR_DST  		0x4b0000dc	/* DMA 3 Current destination	     */
#define DMA3_MASK_TRIGGER	0x4b0000e0	/* DMA 3 Mask trigger		     */

/*
 * clock & power management
 */
#define LOCK_TIME		0x4c000000	/* PLL lock time counter	  */
#define MPLL_CTRL		0x4c000004	/* MPLL Control			  */
#define UPLL_CTRL		0x4c000008	/* UPLL Control			  */
#define CLK_CTRL		0x4c00000c	/* Clock generator control	  */
#define SLOW_CLK_CTRL   	0x4c000010	/* Slow clock control		  */
#define CLK_DIV_CTRL    	0x4c000014	/* Clock divider control	  */
#define CAM_DIV_CTRL    	0x4c000018	/* USB, CAM Clock divider control */

/*
 * gpio contorl
 */
#define GPA_CTRL    		0x56000000	/* Port A control    */
#define GPA_DATA    		0x56000004	/* Port A data	     */
		    		
#define GPB_CTRL    		0x56000010	/* Port B control    */
#define GPB_DATA    		0x56000014	/* Port B data	     */
#define GPB_PUP_CTRL    	0x56000018	/* Pull-up control B */

#define GPC_CTRL    		0x56000020	/* Port C control    */
#define GPC_DATA    		0x56000024	/* Port C data	     */
#define GPC_PUP_CTRL		0x56000028	/* Pull-up control C */
		    		
#define GPD_CTRL    		0x56000030	/* Port D control    */
#define GPD_DATA    		0x56000034	/* Port D data	     */
#define GPD_PUP_CTRL		0x56000038	/* Pull-up control D */
		    		
#define GPE_CTRL    		0x56000040	/* Port E control    */
#define GPE_DATA    		0x56000044	/* Port E data	     */
#define GPE_PUP_CTRL		0x56000048	/* Pull-up control E */
		    		
#define GPF_CTRL    		0x56000050	/* Port F control    */
#define GPF_DATA    		0x56000054	/* Port F data	     */
#define GPF_PUP_CTRL		0x56000058	/* Pull-up control F */
		    		
#define GPG_CTRL    		0x56000060	/* Port G control    */
#define GPG_DATA    		0x56000064	/* Port G data	     */
#define GPG_PUP_CTRL		0x56000068	/* Pull-up control G */
		    		
#define GPH_CTRL    		0x56000070	/* Port H control    */
#define GPH_DATA    		0x56000074	/* Port H data	     */
#define GPH_PUP_CTRL		0x56000078	/* Pull-up control H */
		    		
#define GPJ_CTRL    		0x560000d0	/* Port J control    */
#define GPJ_DATA    		0x560000d4	/* Port J data	     */
#define GPJ_PUP_CTRL		0x560000d8	/* Pull-up control J */


#define RAM_BASE_ADDR		0x30000000
#define EXC_BASE_ADDR		0x33ffff00     
#define MMU_BASE_ADDR		0x33ff8000
#define STACK_BASE_ADDR		0x33ff8000
#define HEAP_END_ADDR	  	0x33ff0000
#define NONCACHE_BASE_ADDR	0x31000000

/*
 * Exception vector
 */
#define EXC_RESET_ADDR		(EXC_BASE_ADDR + 0x0)
#define EXC_UNDEF_ADDR		(EXC_BASE_ADDR + 0x4)
#define EXC_SWI_ADDR	      	(EXC_BASE_ADDR + 0x8)
#define EXC_PABORT_ADDR    	(EXC_BASE_ADDR + 0xc)
#define EXC_DABORT_ADDR    	(EXC_BASE_ADDR + 0x10)
#define EXC_RESERVED_ADDR  	(EXC_BASE_ADDR + 0x14)
#define EXC_IRQ_ADDR	      	(EXC_BASE_ADDR + 0x18)
#define EXC_FIQ_ADDR     	(EXC_BASE_ADDR + 0x1c)


/*
 * Interrupt vector
 */
#define ISR_EINT0		(EXC_BASE_ADDR + 0x20)
#define ISR_EINT1		(EXC_BASE_ADDR + 0x24)
#define ISR_EINT2		(EXC_BASE_ADDR + 0x28)
#define ISR_EINT3		(EXC_BASE_ADDR + 0x2c)
#define ISR_EINT4_7		(EXC_BASE_ADDR + 0x30)
#define ISR_EINT8_23		(EXC_BASE_ADDR + 0x34)
#define ISR_CAM			(EXC_BASE_ADDR + 0x38)		// Added for 2440.
#define ISR_BAT_FLT		(EXC_BASE_ADDR + 0x3c)
#define ISR_TICK		(EXC_BASE_ADDR + 0x40)
#define ISR_WDT_AC97		(EXC_BASE_ADDR + 0x44)
#define ISR_TIMER0		(EXC_BASE_ADDR + 0x48)
#define ISR_TIMER1		(EXC_BASE_ADDR + 0x4c)
#define ISR_TIMER2		(EXC_BASE_ADDR + 0x50)
#define ISR_TIMER3		(EXC_BASE_ADDR + 0x54)
#define ISR_TIMER4		(EXC_BASE_ADDR + 0x58)
#define ISR_UART2		(EXC_BASE_ADDR + 0x5c)
#define ISR_LCD			(EXC_BASE_ADDR + 0x60)
#define ISR_DMA0		(EXC_BASE_ADDR + 0x64)
#define ISR_DMA1		(EXC_BASE_ADDR + 0x68)
#define ISR_DMA2		(EXC_BASE_ADDR + 0x6c)
#define ISR_DMA3		(EXC_BASE_ADDR + 0x70)
#define ISR_SDI			(EXC_BASE_ADDR + 0x74)
#define ISR_SPI0		(EXC_BASE_ADDR + 0x78)
#define ISR_UART1		(EXC_BASE_ADDR + 0x7c)
#define ISR_NFCON		(EXC_BASE_ADDR + 0x80)		// Added for 2440.
#define ISR_USBD		(EXC_BASE_ADDR + 0x84)
#define ISR_USBH		(EXC_BASE_ADDR + 0x88)
#define ISR_IIC			(EXC_BASE_ADDR + 0x8c)
#define ISR_UART0		(EXC_BASE_ADDR + 0x90)
#define ISR_SPI1		(EXC_BASE_ADDR + 0x94)
#define ISR_RTC			(EXC_BASE_ADDR + 0x98)
#define ISR_ADC			(EXC_BASE_ADDR + 0x9c)

#define FIN	0x12000000

extern void exc_undef_handler(void);
extern void exc_swi_handler(void);
extern void exc_pabort_handler(void);
extern void exc_dabort_handler(void);
extern void exc_int(void);

/* gpio_init -
 * follow the configuration order for setting the ports, if any. 
 * 1) setting value(GPnDAT) 
 * 2) setting control register  (GPnCON)
 * 3) configure pull-up resistor(GPnUP)  
 */
extern void gpio_init();

extern void cal_cpu_bus_clk(void);
#endif /* end of __S3C2440_H__ */
